Explore the whole process of semiconductor manufacturing: from wafer processing to packaging and testing

Each semiconductor product requires hundreds of processes, the entire manufacturing process is divided into eight steps: wafer processing - oxidation - lithography - etching - thin film deposition - interconnect - test - packaging.

The first step wafer processing

All national semiconductor technology process begins with a grain of sand! This is because the silicon contained in this sand is the raw material needed to produce wafers. A wafer is a thin, round piece of silicon (Si) or gallium arsenide (GaAs) formed during the dicing of a single-crystal column. To extract high-purity silicon material development requires us to use silica sand, a learning silicon dioxide content can be as high as 95% of the special education materials, but also a production of wafers, including the main raw materials. The wafer processing method is the process of obtaining a solution to the above mentioned wafers through the production company.

Ingot Casting

Sand is first heated to separate the carbon monoxide from the silicon,wafer test and the process is repeated until the student obtains ultra-high purity electronic grade silicon (EG-Si). The melting of high-purity silicon into a liquid, which is then solidified into single crystals and solid structures called ingots, is the first step in the manufacture of semiconductor materials in China. Silicon ingots (pillars) can be made with a low level of technical precision, down to the nanometer level, and are widely researched and applied by the Lift-and-Pull method.

Ingot cutting

After the previous step is completed, the ends of the ingot are cut off with a diamond and then sliced into thin slices of a certain thickness. The diameter of the ingot determines the size of the wafer.wafer level testing Larger and thinner wafers can be split into more usable units, which helps to reduce production costs. After the ingots are cut, "flat areas" or "dents" are marked on the sheet so that the direction of the process can be set on this basis in subsequent steps.

Wafer Surface Polishing

The wafer obtained by the above cutting process is called "bare", i.e. the raw material wafer. The surface of the bare film is not flat and cannot be directly printed on the circuit pattern. Therefore, it is necessary to remove surface defects by grinding and chemical etching, then polish to form a smooth surface, and wash to remove residual contaminants to obtain a clean surface for the finished wafer.

Step 2 Oxidation

The function of the oxidation process is to form a protective film on the wafer surface. It protects the wafer from chemical impurities, prevents leakage currents from entering the circuit, prevents diffusion during ion implantation, and prevents the wafer from slipping during the etching process.

The first step in the oxidation process is to remove impurities and contaminants, which requires us to go through a four-step process of removing impurities such as organics, metals and evaporating residual water. Once the cleaning is complete, companies can place the wafers at temperatures between 800 and 1200 degrees Celsius as well as in an environment where a layer of silicon dioxide (i.e., "oxide") is formed by studying the flow assets of oxygen or vapor on the surface of the wafer. Oxygen diffusion students study the ability of the oxide layer to react with the silicon to form oxide layers with different cultural thicknesses, which can be measured after the oxidation technique is complete.

Dry and wet oxidation depend on the oxidizing agent in the oxidation reaction, and the thermal oxidation process can be divided into dry and wet oxidation. The former uses pure oxygen to create a silica layer which is thin and slow, while the latter requires both oxygen and highly soluble water vapor, the latter possessing the property of rapid growth but a relatively thicker and less dense protective layer.

In addition to the oxidizer,failure analysis there are a number of other relevant variables that affect the thickness of the silica layer. First, the wafer structure analysis and its work surface defects and the existence of different concentrations of internal doping will have a direct impact as well as the rate of generation of the oxide layer. In addition, the higher the pressure and temperature that can be generated by the oxidation technology equipment, the faster the generation of the oxide layer. During the oxidation process, it is also necessary to use dummy wafers depending on the position of the wafers in the cell to protect the wafers and reduce the difference in oxidation degree.

Step 3 Photolithography

Photolithography is the process of "printing" a circuit pattern on a wafer with light, which can be understood as drawing a planar pattern on the surface of the wafer for semiconductor manufacturing. The higher the precision of the circuit pattern, the higher the integration of the finished chip, and advanced lithography must be used. Specifically, lithography can be divided into three steps: photoresist coating, exposure and development.

Coating

The first step in creating circuits on a wafer is to coat the oxide layer with a photoresist. The photoresist turns the wafer into "photo paper" by changing its chemical properties. The thinner the layer of photoresist on the wafer surface, the more uniform the coating and the finer the pattern that can be printed. This step can be performed by the "spin-coating" method. Photoresists are categorized as positive or negative depending on their reactivity to light (ultraviolet). The former decomposes and disappears when exposed to light, leaving the pattern in the unexposed area, while the latter converges when exposed to light, causing the pattern in the exposed area to appear.

Exposure

After covering a wafer with a photoresist film, it is possible to print working circuits directly through internally controlled ambient light exposure, a development process known as "exposure". This development process is called "exposure." Our instructors can selectively study and analyze the light through a network of exposure technology devices at the same time, and when the light passes through the mask containing the circuit pattern, the circuit can be printed onto the wafer coated with the photoresist film underneath.

The finer the print during the exposure process, the more components the final chip can hold, which helps to increase productivity and reduce the cost of individual components. A new technology that is currently receiving a lot of attention in this area is EUV lithography. Together with strategic partners ASML and IMEC, PanForest Group has developed a new dry film photoresist technology. This technology can significantly improve the productivity and yield of EUV lithography by increasing the resolution, which is a key factor in fine-tuning circuit widths.

Developing

The step after exposure is to spray a developer on the wafer to remove the photoresist from the uncovered areas of the pattern, thus allowing the printed circuit pattern to emerge. Once development is complete, it is necessary to check the quality of the circuit pattern by means of various measuring devices and optical microscopes.

Step 4: Etching

After photolithography of the circuit diagram on the wafer, an etching process is used to remove any excess oxide film, leaving only the semiconductor circuit diagram. To do this, you will need to use a liquid, gas, or plasma to remove selected excess. Depending on the substance used, there are two main types of etching methods: wet etching, which uses a chemical reaction with a specific chemical solution to remove the oxide film; and dry etching, which uses a gas or plasma.

Wet etching

Wet etching using a chemical solution to remove the oxide film has the advantages of low cost, fast etching speed and high productivity. However, wet etching is isotropic, i.e., its velocity is the same in any direction. This results in the mask (or sensitive film) and the etched oxide film not being perfectly aligned, making it difficult to process very fine circuit diagrams.

Dry Etching

Dry etching can be categorized into three ways different types of businesses as follows. The first is chemical etching, which uses an etching gas (mainly hydrogen fluoride). Like wet etching, this method of teaching research is also anisotropic, which means that it is also unsuitable for fine etching that can be managed.

The second method is physical sputtering, in which ions in the plasma are used to strike and remove excess oxide. As an anisotropic etching method, sputter etching has a different etching rate in the horizontal and vertical directions, and is therefore more accurate than chemical etching. However, the disadvantage of this method is that the etching rate is slow because it relies entirely on physical reactions caused by ionic collisions.

The last and third method is reactive ion etching (RIE).RIE combines the first two methods, i.e., the plasma is used for ionization physical etching at the same time, the free radicals generated after plasma activation are used for chemical etching.RIE in addition to the etching speed exceeds that of the first two methods, it can also take advantage of the characteristics of the anisotropy of ions to achieve high-precision graphic etching.

Currently, dry etching is widely used to improve the yield of fine semiconductor circuits. It is critical to maintain uniformity of whole wafer etching and to improve etching speed. State-of-the-art dry etching equipment is supporting the production of logic and memory chips with the most advanced performance.

Step 5: Thin Film Deposition

To create miniature devices inside the chip, we need to continuously deposit multiple layers of film and remove the excess through etching, as well as add some material to separate the different devices. Each transistor or memory cell is built step by step through this process. The term "thin film" here refers to a "film" that is less than 1 micron (micron, one millionth of a meter) thick, and cannot be made by ordinary machining methods. The process of placing a thin film containing the desired molecular or atomic units on a wafer is called "deposition".

To form a multilayered semiconductor structure, the country needs to create system device stacks, i.e. alternating layers of thin metallic (conductive) and dielectric (insulating) films on the surface of a wafer, after which the excess is removed by repeating the etching process and a three-dimensional spatial structure is formed. The technologies available for the deposition process include chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD), and methods based on these data can be developed into dry and wet deposition.

Chemical Vapor Deposition

In chemical vapor deposition, a precursor gas reacts in a reaction chamber to form a thin film that adheres to the wafer surface and a by-product that is removed from the chamber. Plasma-enhanced chemical vapor deposition utilizes a plasma to generate reaction gases. This method reduces the reaction temperature and is well suited for temperature sensitive structures. The use of plasma also reduces the amount of deposition and typically produces higher quality films.

Atomic Layer Deposition

Atomic Layer Deposition forms thin films by depositing only a few atomic layers at a time. The key to this method is to cycle the separate steps in a certain order and maintain good control. The first step is to coat the surface of the wafer with a precursor, and then different gases are passed through to react with the precursor to form the desired substance on the wafer surface.

Physical vapor deposition

As the name suggests, physical vapor deposition refers to the formation of thin films by physical means. Sputtering is a physical vapor deposition process in which target atoms are sputtered by argon plasma bombardment and deposited on the wafer surface to form a thin film. In some cases, ultraviolet thermal processing (UVTP) and other techniques can be used to treat the deposited film and improve its properties.

Step 6 Interconnections

Semiconductors have an electrical conductivity between conductors and non-conductors (i.e., insulators), allowing us to have complete control over electrical currents. Transistors and other components can be built by wafer-based lithography, etching, and deposition processes, but they need to be connected for power and signal transmission and reception.

Metals are used to control circuit interconnections because of their development to be conductive. Metals used in semiconductors need to constantly fulfill the following operating conditions:

* Low resistivity: Since metal circuits require current transmission, the metals in them should have low resistance.

Thermo-chemical stability: The properties of the metal material must remain unchanged during the metal interconnect process.

* High Reliability: With the advancement of integrated circuit technology, even a small amount of metal interconnect material must be durable enough.

Manufacturing Cost: Even if the first three conditions have been met, if the material cost is too high, it will not be sufficient for mass production.

The interconnect process has been studied primarily through the use of two substances, aluminum and copper.

Aluminum Interconnect Process

The aluminum interconnect process begins with aluminum deposition, photoresist application, exposure and development, followed by etching to selectively remove any excess aluminum and photoresist before the oxidation process begins. The process of lithography, etching and deposition is repeated until the interconnect is complete.

In addition to its excellent electrical conductivity, aluminum is easy to photolithograph, etch and deposit. In addition, it is low cost and adheres well to oxide films. Its disadvantages are easy corrosion and low melting point. In addition, in order to prevent connection problems caused by the reaction between aluminum and silicon, it is necessary to separate aluminum from the wafer by adding a metal deposit, which is called a "barrier metal.

Aluminum circuits are formed by deposition. Once the wafer enters the vacuum cavity, a thin film of aluminum particles is formed and adheres to the wafer. This process is called "vapor deposition (VD)" and includes chemical vapor deposition and physical vapor deposition.

Copper Interconnect Process

As semiconductor process precision increased and device sizes decreased, the connection speed and electrical characteristics of aluminum circuits became inadequate, and new conductors were sought to meet size and cost requirements. The first reason copper can replace aluminum is that it has lower resistance, so faster device connection speeds can be achieved. Second, copper is more reliable because it is more resistant than aluminum to electromigration, the movement of metal ions as current flows through the metal.

However, copper does not readily form a compound, making it difficult for companies to remove it by vaporizing it as and removing it from the wafer surface. In response to this social problem in China, we no longer etch copper, but can deposit and etch dielectric materials, so that students can be in the desired place without the formation of metal lines composed of trenches and access holes graphic, and then fill the copper into the aforementioned "graphic" can be obtained to realize the interconnection of the network, and the final filling process is known as the The final filling process is known as the "inlay process".

As the copper atoms continue to diffuse into the dielectric, the insulation of the latter is reduced and a barrier layer is formed to prevent further diffusion of the copper atoms. A thin layer of copper seeds is then formed on top of the barrier layer. This step is followed by electroplating, in which copper is used to fill the high spreading ratio pattern. Excess copper can be removed by chemical-mechanical planarization of metals (CMP-rrb-process), and upon completion an oxide film can be deposited, while excess film can be removed by photolithography and etching processes. The whole process needs to be repeated until the copper interconnect is complete.

As you can see from the comparison above, the difference between the copper interconnect and the aluminum interconnect is that the excess copper is removed using metal CMP, not etching.

Step 7 Testing

The main goal of testing is to verify that the quality of the semiconductor chip meets certain standards so that defective products can be eliminated and the reliability of the chip can be improved. Additionally, defective products that are tested do not make it to the packaging step, helping to save costs and time. Electronic core sorting (EDS) is a wafer-specific test method.

EDS is a process that improves semiconductor yield by testing the electrical characteristics of each chip in the wafer state, and can be divided into the following five steps.

01 Electrical Parameter Monitoring (EPM)

EPM is the first step in semiconductor chip testing. This step tests each device (including transistors, capacitors, and diodes) required for semiconductor integrated circuits to ensure that its electrical parameters are up to standard. the primary role of EPM is to provide measured electrical data that will be used to improve the efficiency of the semiconductor manufacturing process and product performance (without detecting defective products).

02 Wafer Aging Test

Semiconductor defect rates come from two sources, the manufacturing defect rate (which is higher upfront) and the subsequent defect rate throughout the life cycle. Wafer aging test refers to the testing of wafers at a certain temperature and ACu002FDC voltage, so as to detect possible defective products at an early stage, i.e., to improve the reliability of the final product by detecting potential defects.

03 Testing

After the aging test is completed, the semiconductor chip is connected to the test device by means of a probe card. After this, the temperature, speed and movement of the wafer can be tested to verify the function of the semiconductor. For detailed test procedures, please refer to the table.

04 Repair

Repair is the most important test step because some bad chips can be repaired by simply replacing the defective component.

05 Dotting

Chip technologies that fail the Improved Electrical Controls test have already been sorted out in the previous important steps, but markings need to be added to effectively differentiate them. Whereas in the past we needed to mark defective chips with special ink to ensure that they could be recognized by the naked eye, today the system can sort them in an automated pattern based on actual test and analysis data values.

Step 8 Encapsulation

Equal-sized square chips (also called "single chips") are formed on wafers that have been processed in the previous stages. The next step is to obtain individual chips by cutting. Freshly cut chips are very fragile and cannot exchange electrical signals and need to be handled separately. This process is called packaging and consists of forming a protective shell around the outside of the semiconductor chips so that they can exchange electrical signals with the outside. The entire packaging process is divided into five steps, namely wafer sawing, single chip placement, interconnection, molding and package testing.

01 Wafer sawing

In order to cut numerous densely arranged chips from a wafer, we must first carefully "sand" the backside of the wafer until its thickness meets the needs of the packaging process. After grinding, we can cut along the cut lines on the wafer until the semiconductor chips are separated.

There are three types of wafer sawing techniques: blade cutting, laser cutting, and plasma cutting. Blade dicing involves cutting the wafer with a diamond blade. This method is prone to frictional heat and debris, which can damage the wafer. Laser cutting is more accurate and can easily handle the thickness of the wafer or have a small scribe pitch. Plasma dicing is based on the principle of plasma etching, which can be applied even if the spacing between the stroke lines is small.

02 Individual wafer attachment

After all chips have been separated from the wafer, we need to attach the individual chips (single wafers) to a substrate (lead frame). The purpose of the substrate is to protect the semiconductor chips and allow them to exchange electrical signals with external circuits. Liquid or solid tape adhesives can be used to attach the chips.

03 Interconnection

After attaching the chip to the substrate, our country still needs to connect the contacts between the two to actually exchange an electrical signal. There are two connection methods that can be used for this step: lead bonding using thin metal wires and flip chip bonding using spherical nuggets of gold or tin. Leaded wire bonding is a traditional Chinese teaching method, and flip chip bonding technology companies can continue to accelerate the development of semiconductor material manufacturing.

04 Molding

After a semiconductor chip is connected, a package needs to be added to the outside of the chip through the forming process to protect the semiconductor integrated circuit from external conditions such as temperature and humidity. The semiconductor chip and epoxy mold material (EMC) are placed in a mold and sealed. The sealed chip is the final form.

05 Package Testing

A chip that already has a final form must pass a final defect test. The final test is all about finished semiconductor chips. They are placed in test equipment and set to different conditions such as voltage, temperature and humidity to perform electrical, functional and speed tests. The results of these tests can be used to detect defects and improve product quality and productivity.

Evolution of Packaging Technology

Packaging technology has undergone many technological innovations over the years as chip sizes have decreased and performance requirements have increased. Some of the future-proof packaging technologies and solutions include the use of deposition technologies for traditional back-channel processes such as wafer-level packaging (WLP), bumping and rerouting layer (RDL) technologies, as well as etching and cleaning technologies for fabricating front-end wafers.

What is advanced packaging?

Traditional packaging involves cutting each chip out of the wafer and placing it into a mold. Wafer Level Packaging (WLP), on the other hand, is a type of advanced packaging technology that involves directly packaging a chip that is still on the wafer. the process of WLP involves packaging and testing, and then separating all of the molded chips from the wafer at one time. The advantage of WLP over traditional packaging is lower production costs.

Advanced Technology Packaging can be categorized into 2D, 2.5D and 3D packages.

Smaller 2D Packages

As mentioned earlier, the main use of the packaging process consists of sending signals out from the semiconductor chip to the outside, where bumps are formed on the wafer that are contact points for sending input/output signals. These bumps are of two types: fan-in and fan-out. The former fans in on the inside of the chip, while the latter fans out on the outside of the chip. We call input/output signal I/O (Input/Output) and input/output I/O counts, which are important for determining the packaging method. If the I/O count is low, the in-fan packaging process is used. This process is also referred to as chip-scale packaging (CSP) or wafer-level chip-size packaging (WLCSP) because there is very little change in chip size after packaging. If the I/O count is high, a fan-out package is often used and requires RDLs in addition to bumps when sending signals.This is known as fan-out wafer level packaging (FOWLP).

2.5D Packaging

2.5D packaging technology allows two or more types of chips to be placed in a single package while allowing signals to be transmitted laterally, which improves the size and performance of the package. The most widely used 2.5D packaging method is the placement of memory and logic chips into a single package via silicon inserts. 2.5D packaging requires core technologies such as through-silicon vias (TSVs), microbumps, and small-pitch RDLs.

3D Packaging

3D packaging technology allows two or more chips to be packaged together while allowing signals to travel vertically. This technology is suitable for semiconductor chips with decreasing I/O counts; TSVs can be used for high I/O count chips and lead bonding can be used for low I/O count chips, resulting in a signal system with vertically aligned chips. The core technologies for three-dimensional packaging include TSV technology and micro-bumping technology.

So far, the semiconductor product manufacturing "wafer processing - oxidation - photolithography - etching - thin film deposition - interconnection - test - packaging" eight steps have been introduced, from "sand" to "chip From "sand" to "chip", semiconductor technology is staging a realistic version of the "stone into gold".

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